Achieving a high degree of synchronization between data signals and clocks can be a significant aspect to the reliable transmission of data between integrated circuit devices, such as integrated circuit memory devices (e.g., DRAM devices) and memory controllers that transmit data to and from the integrated circuit memory devices. To achieve such high levels of synchronization between data signals and clocks, phase-locked loop (PLL) integrated circuits and delay-locked loop (DLL) integrated circuits have been developed to synchronize the timing of internal clocks (ICLK) with external clocks (ECLK).
FIG. 1 is a timing diagram that illustrates the synchronization of data transmission under three scenarios. In the first scenario, an external clock (ECLK) having a non-uniform duty cycle is used to synchronize the receipt of data DATA by an integrated circuit device (e.g., memory controller receiving data from a DRAM device) at a single data rate (SDR). In this first scenario, the use of a rising (or falling edge) of the external clock ECLK to latch-in (i.e., capture) the received data DATA can be performed reliably because each rising edge (or falling edge) is separated from a subsequent rising edge (or falling edge) by a fixed amount of time equivalent to one full period of the external clock ECLK. Accordingly, the failure of the external clock ECLK to have a uniform duty cycle typically does not influence the reliability of data synchronization. However, in the second scenario, when the external clock ECLK is used to synchronize data capture at a dual data rate (DDR), then the non-uniform duty cycle associated with the external clock ECLK will typically operate to limit the reliability of data capture. In particular, FIG. 1 illustrates how a rising edge of the external clock ECLK is subject to a much smaller data window (F0, F1, F2, . . . ) than the falling edge of the external clock ECLK, which is subject to a larger data window (S0, S1, S2, . . . ). The presence of this smaller data window associated with the rising edges of the external clock ECLK operates to limit the maximum frequency of the external clock ECLK that may be used to reliably capture incoming data. To address these problems associated with synchronizing data at dual data rates when non-uniform duty cycle are present, a duty cycle correction circuit (DCC circuit) may be used to convert an external clock ECLK having a non-uniform duty cycle into an internal clock ICLK having a uniform duty cycle. As illustrated at the bottom of FIG. 1, the use of an internal clock ICLK having a uniform duty cycle may be used to more reliably capture incoming data by equalizing the widths of the data windows associated with the rising and falling edges of the clock (i.e., equalize F0, F1, F2, . . . with S0, S1, S2, . . . ).
FIG. 2 illustrates a block diagram of an internal clock generator 200 having an analog duty cycle correction (DCC) circuit therein. This clock generator 200 includes a delay-locked loop 210 and an analog duty cycle correction (DCC) circuit 230, as described more fully by Korean Patent Publication No. 2003-0052650. The delay-locked loop 210 is configured to generate a preliminary internal clock ICLKP from an external clock ECLK. This preliminary internal clock ICLKP may have the same non-uniform duty cycle as the external clock ECLK. The preliminary internal clock ICLKP is provided as an input to the duty cycle correction circuit 230, which generates an internal clock ICLK having a uniform duty cycle. Unfortunately, the use of an analog duty cycle correction circuit may operate to limit the performance characteristics of the clock signal generator 200 upon start-up (i.e., power up) because of inherent start-up delays (e.g., capacitor charging delays). Accordingly, notwithstanding the DCC circuit 230 of FIG. 2, there continues to be a need for improved clock generators having improved operating characteristics.